EPEE is an efficient and flexible host-FPGA PCIe communication library. EPEE suports various generations of Xilinx FPGAs with up to 26.24 Gbps half duplex and 43.02 Gbps fullduplex aggregata throughput in the PCIe Gen X8 mode (tested in Xilinx VC707 evaluation board).
The EPEE library consists of a software component and an FPGA (hardware) component, each includes a core layer and an extension layer as shown in the upper figure. It also includes a PCI driver that handles the interaction between the software core layer and the PCIe bus. At the FPGA side, the hard PCIe IP core (provided by FPGA vendors) handles the interactions between the hardware core layer and the PCIe bus.
Website of RAW group: http://cecaraw.pku.edu.cn/
EPEE website: http://cecaraw.pku.edu.cn/Eng_EPEE.html
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